FIG. 1A shows a conventional static random access memory ("SRAM") cell 50, which is represented on a transistor level at 50A and on a more general gate level at 50B. On the transistor level, cell 50 includes PMOS transistors M1 and M2 and NMOS transistors M3 through M6. Transistors M1 and M3 are configured as a conventional inverter, which is shown as U2 in FIGURE 50B. Likewise, transistors M2 and M4 are configured as a conventional static inverter, which is shown as U1 in FIG. 50B. Inverter M1/M3 (U2) is cross-coupled with inverter M2/M4 (U1) to form the memory storage portion of cell 50. The input of inverter M2/M4 (U1), which is connected to the output of inverter M1/M3 (U2) provides a DATA storage node, and the input of inverter M1/M3 (U2), which is connected to the output of inverter M2/M4 (U1), provides a Not DATA storage node. Transistors M5 and M6 function as switches to control access to the DATA/Not DATA nodes from a differential BIT/Not BIT input. Their gates are connected to a Word Line ("WL") signal that when active (high) enables writing to and reading from the DATA/Not DATA memory cell nodes.
The two cross-coupled PMOS pull-up transistors, M1 and M2, retain a "1" value (at DATA, Not DATA) when written into the cell. These cross-coupled p-devices are designed to be strong enough to retain a 1 value in the cell indefinitely without any external refresh mechanism. However, if the P-devices are too weak due to a fabrication defect or a connection to either of the P devices is missing, the SRAM cell will no longer be able to hold its data indefinitely. The resulting fault in defective cell is referred to as a data retention fault (DRF) or a cell stability fault, depending on its severity. Thus, all SRAMs require some form of data retention and cell stability testing.
Traditionally, testing large static CMOS memory arrays for data retention faults (DRFs) and cell stability faults had been a time consuming and expensive effort. Test methods had also been partial in their test coverage. The algorithmic test methods used for detecting these faults were primarily functional in nature; that is they checked the cell stability or retention in a functional manner. These algorithmic test methods were time consuming and required extensive characterization of silicon to determine the worst case test conditions. Fortunately, improved test methodologies have been developed, which address these problems. One such test method is known as Weak Write Test Mode ("WWTM"). for additional information relating to weak write testing, as well as on more traditional methods, reference may be made to Meixner and Banik, Weak Write Test Mode: An SRAM Cell Design Stability Design For Test Technique, IEEE 0-78033540-6/96 (1996), which is hereby incorporated by reference into this specification.
A weak write test is active--in contrast to former tests, which were passive. A WWTM circuit actively attempts to weakly overwrite a cell. It is only capable of overwriting an unstable cell due to the presence of a defect. If the cell can be weakly overwritten, it is assessed to be defective, and if it cannot be weakly overwritten, it is deemed healthy. A weak write test can be used to test an array of memory in much less time than the former passive tests.
FIG. 1B shows a WWTM circuit 60 for testing SRAM cell 50. Weak write tests are implemented with a row of WWTM circuits attached to the bit line pairs of a memory array. WWTM circuit 60 generally includes a PMOS transistor Ma, an NMOS transistor Mb, and pass gate MOS devices Mc through Mf. Transistor Ma provides a high signal to a High node of the circuit 60. Conversely, transistor Mb provides a low signal (ground) to a Low node. The WWTM circuit 60 includes BIT and Not BIT outputs that are respectively connected across the BIT and Not BIT inputs of he SRAM cell 50. The BIT output is selectively connected to the High node through pass gate Mc and selectively connects the Low node through pass gate Mf. Alternatively, the Not BIT output is selectively connected to the High node through pass gate Md and selectively connected to the Low node through pass gate Me. A WR1 input is connected to the gates of Mc and Mf for selecting them in order to weak write a "1" (i.e., apply a weak "1") at the memory cell. Conversely, a WR0 input is connected to the gates of pass gates Md and Me for selecting them in order to weak write a "0" at the memory cell. Transistors Ma and Mb are sized so that circuit 60 is not strong enough to override the value in a healthy cell yet strong enough to override the value in a defective cell.
WWTM circuit 60 may be used for implementing a weak write test in the following manner. Initially, a background of "0"s are written into a memory cell array. The WWTM circuit 60 is enabled, and a weak write "1" is written to the array, word line by word line, for a preselected time. WWTM circuit 60 is then disabled, and the cells are read to determine if any cell has been overwritten. A background of solid "1"s are then written into the array. The WWTM circuit 60 is once again enabled, but this time, weak write "0"s are written to the cells word line by word line for a preselected time. Circuit 60 is disabled, and the cells are read. The cells that have been written over--either with "1"s or "0"s--are identified as being defective.
The preselected time for weak writing to a cell is longer than the time for a normal write operation. For example, in a weak write test mode, a weak write to a cell can occur from 20 to 50 times longer than a typical write cycle time. With the types of processors currently being designed, such required weak write testing time is still far shorter than the milliseconds or even seconds that were required with the previous passive methods.
In a typical arrangement, the WWTM circuit 60 is attached at the end of each SRAM cell column in a memory array. Unfortunately, the WWTM circuit is about 1.5 times the size of a normal memory cell 50. Thus, the area consumed by the WWTM circuits for a memory array is problematic. For example, with arrays having 32 rows in each column, the incorporation of WWTM circuits into memory arrays increases their required size by almost 5%. This is unacceptable in applications (e.g., microprocessor cache) where area is a critical issue.
Accordingly, what is needed is an improved scheme for implementing weak write testing.